diff options
| author | Roland Haas <rhaas@tapir.caltech.edu> | 2013-05-12 11:53:20 -0700 |
|---|---|---|
| committer | Roland Haas <rhaas@tapir.caltech.edu> | 2013-05-12 11:53:20 -0700 |
| commit | a4dc204e712f58cabfc270a5cb158ff9664485cf (patch) | |
| tree | af3e4097920e0ff70b25277c0c629cc032e5798a /Carpet/LoopControl/param.ccl | |
| parent | d2265e829d3e1f3f9ab19bd5b805b82c7f79942f (diff) | |
LoopControl: disable smt by default
We currently have issues with this switch changing results of
computation when used in combination with openmp and using all cores.
Diffstat (limited to 'Carpet/LoopControl/param.ccl')
| -rw-r--r-- | Carpet/LoopControl/param.ccl | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/Carpet/LoopControl/param.ccl b/Carpet/LoopControl/param.ccl index acb46857d..71329ca71 100644 --- a/Carpet/LoopControl/param.ccl +++ b/Carpet/LoopControl/param.ccl @@ -37,9 +37,10 @@ KEYWORD initial_setup "Initial configuration" STEERABLE=always # NOTE: # - Intel chips divide the D1 cache into two, one for each hyperthread. # The cache is thus not shared! +# This is off by default since it seems to affect results on intel processors. BOOLEAN use_smt_threads "Place SMT threads close together" STEERABLE=always { -} "yes" +} "no" BOOLEAN align_with_cachelines "Align innermost loops with cache line size" STEERABLE=always { |