diff options
| -rw-r--r-- | Carpet/LoopControl/param.ccl | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/Carpet/LoopControl/param.ccl b/Carpet/LoopControl/param.ccl index acb46857d..71329ca71 100644 --- a/Carpet/LoopControl/param.ccl +++ b/Carpet/LoopControl/param.ccl @@ -37,9 +37,10 @@ KEYWORD initial_setup "Initial configuration" STEERABLE=always # NOTE: # - Intel chips divide the D1 cache into two, one for each hyperthread. # The cache is thus not shared! +# This is off by default since it seems to affect results on intel processors. BOOLEAN use_smt_threads "Place SMT threads close together" STEERABLE=always { -} "yes" +} "no" BOOLEAN align_with_cachelines "Align innermost loops with cache line size" STEERABLE=always { |