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authoreschnett <eschnett@105869f7-3296-0410-a4ea-f4349344b45a>2011-08-25 17:40:05 +0000
committereschnett <eschnett@105869f7-3296-0410-a4ea-f4349344b45a>2011-08-25 17:40:05 +0000
commit802b82837b5b37b7c76ee807939bbffe76f17fdd (patch)
treecc18cef877eb8067bdbd202a696112cf2d6e0431 /src/vectors-4-SSE.h
parentb075a3dfcf5aaa72c086d7896ab0c975f42d04c2 (diff)
Suggest asm statements to support SSE4a with Intel compilers.
Indent vector architecture definitions. git-svn-id: https://svn.cct.lsu.edu/repos/numrel/LSUThorns/Vectors/trunk@30 105869f7-3296-0410-a4ea-f4349344b45a
Diffstat (limited to 'src/vectors-4-SSE.h')
-rw-r--r--src/vectors-4-SSE.h6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/vectors-4-SSE.h b/src/vectors-4-SSE.h
index 2f55183..dbf0cce 100644
--- a/src/vectors-4-SSE.h
+++ b/src/vectors-4-SSE.h
@@ -21,11 +21,11 @@
#ifdef __SSE4_1__
-#define vec4_architecture "SSE4.1 (32-bit precision)"
+# define vec4_architecture "SSE4.1 (32-bit precision)"
#elif defined(__SSE4A__)
-#define vec4_architecture "SSE4A (32-bit precision)"
+# define vec4_architecture "SSE4A (32-bit precision)"
#else
-#define vec4_architecture "SSE (32-bit precision)"
+# define vec4_architecture "SSE (32-bit precision)"
#endif
// Vector type corresponding to CCTK_REAL