diff options
author | Erik Schnetter <schnetter@gmail.com> | 2013-01-16 14:43:47 -0500 |
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committer | Erik Schnetter <schnetter@gmail.com> | 2013-01-16 14:43:47 -0500 |
commit | 1cddd960d62da42ccd111022f1326740f688b48d (patch) | |
tree | 5c0c591e8fca50868ae5f80b703c4422eef3df30 /Carpet/CarpetLib/param.ccl | |
parent | f07af2a351c2096f84487b13c114a1925755eafb (diff) |
CarpetLib: Rewrite array padding
Obtain cache information from thorn hwloc.
Align allocated memory manually if operator new returns unaligned memory.
Diffstat (limited to 'Carpet/CarpetLib/param.ccl')
-rw-r--r-- | Carpet/CarpetLib/param.ccl | 95 |
1 files changed, 2 insertions, 93 deletions
diff --git a/Carpet/CarpetLib/param.ccl b/Carpet/CarpetLib/param.ccl index c13d54ba1..6adccca98 100644 --- a/Carpet/CarpetLib/param.ccl +++ b/Carpet/CarpetLib/param.ccl @@ -211,100 +211,9 @@ BOOLEAN use_mpi_ssend "Use MPI_Ssend instead of MPI_Isend" STEERABLE=always -# Memory and cache information -- this is machine dependent and should -# be determined at run time or set via simfactory - -CCTK_INT vector_size "vector size" STEERABLE=recover -{ - 0 :: "unknown" - 1:* :: "" -} 0 - -CCTK_INT D1size "level 1 data cache" STEERABLE=recover -{ - 0 :: "unknown" - 1:* :: "" -} 0 -CCTK_INT D1linesize "level 1 data cache" STEERABLE=recover -{ - 0 :: "unknown" - 1:* :: "" -} 0 -CCTK_INT D1assoc "level 1 data cache" STEERABLE=recover -{ - 0 :: "unknown" - 1:* :: "" -} 0 - -CCTK_INT L2size "level 2 unified cache" STEERABLE=recover -{ - 0 :: "unknown" - 1:* :: "" -} 0 -CCTK_INT L2linesize "level 2 unified cache" STEERABLE=recover -{ - 0 :: "unknown" - 1:* :: "" -} 0 -CCTK_INT L2assoc "level 2 unified cache" STEERABLE=recover -{ - 0 :: "unknown" - 1:* :: "" -} 0 - -CCTK_INT L3size "level 3 unified cache" STEERABLE=recover -{ - 0 :: "unknown" - 1:* :: "" -} 0 -CCTK_INT L3linesize "level 3 unified cache" STEERABLE=recover -{ - 0 :: "unknown" - 1:* :: "" -} 0 -CCTK_INT L3assoc "level 3 unified cache" STEERABLE=recover -{ - 0 :: "unknown" - 1:* :: "" -} 0 - -CCTK_INT TLB_D1entries "level 1 TLB cache" STEERABLE=recover +BOOLEAN pad_to_cachelines "Pad arrays to the cache line size (only when VECTORISE_ALIGNED_ARRAYS is set)" STEERABLE=recover { - 0 :: "unknown" - 1:* :: "" -} 0 -CCTK_INT TLB_D1pagesize "level 1 TLB cache" STEERABLE=recover -{ - 0 :: "unknown" - 1:* :: "" -} 0 -CCTK_INT TLB_D1assoc "level 1 TLB cache" STEERABLE=recover -{ - 0 :: "unknown" - 1:* :: "" -} 0 - -CCTK_INT TLB_L2entries "level 2 TLB cache" STEERABLE=recover -{ - 0 :: "unknown" - 1:* :: "" -} 0 -CCTK_INT TLB_L2pagesize "level 2 TLB cache" STEERABLE=recover -{ - 0 :: "unknown" - 1:* :: "" -} 0 -CCTK_INT TLB_L2assoc "level 2 TLB cache" STEERABLE=recover -{ - 0 :: "unknown" - 1:* :: "" -} 0 - -CCTK_INT pagesize "size of a memory page" STEERABLE=recover -{ - 0 :: "unknown" - 1:* :: "" -} 0 +} "yes" |