Changed the default for boolean parameter PUGH::padding_active from "yes" to

"no" because it doesn't seem to be doing any good on Intel processors and
actually decreases performance on Opterons.


git-svn-id: http://svn.cactuscode.org/arrangements/CactusPUGH/PUGH/trunk@458 b61c5cb5-eaca-4651-9a7a-d64986f99364

1 files changed, 1 insertions, 1 deletions

diff --git a/param.ccl b/param.ccl
index 3b5bcda..fa90b86 100644
--- a/param.ccl
+++ b/param.ccl
@@ -154,7 +154,7 @@ INT processor_topology_3d_z "No of Procs in X direction" STEERABLE = RECOVER
 
 BOOLEAN padding_active "Pad 3D arrays so they line up on cache lines?"
 {
-} yes
+} no
 
 
 INT padding_cacheline_bits "Number of bits which have to be unique to pad properly for cache lines"