diff options
| author | Mans Rullgard <mans@mansr.com> | 2011-03-12 22:17:14 +0000 |
|---|---|---|
| committer | Mans Rullgard <mans@mansr.com> | 2011-04-05 01:11:16 +0100 |
| commit | 5f2e6c0fd11f34ba7cd013a0b22d7bd0d60613b8 (patch) | |
| tree | 6b1bc81fce4d5816756894a133a41472a90326f9 /libavcodec/arm | |
| parent | 2310ee4b1cca48609d06774b7c3c70a5f38f3473 (diff) | |
ac3enc: NEON optimised extract_exponents
Signed-off-by: Mans Rullgard <mans@mansr.com>
Diffstat (limited to 'libavcodec/arm')
| -rw-r--r-- | libavcodec/arm/ac3dsp_init_arm.c | 2 | ||||
| -rw-r--r-- | libavcodec/arm/ac3dsp_neon.S | 20 |
2 files changed, 22 insertions, 0 deletions
diff --git a/libavcodec/arm/ac3dsp_init_arm.c b/libavcodec/arm/ac3dsp_init_arm.c index 92e4a4f291..fd78e1e6a4 100644 --- a/libavcodec/arm/ac3dsp_init_arm.c +++ b/libavcodec/arm/ac3dsp_init_arm.c @@ -28,6 +28,7 @@ int ff_ac3_max_msb_abs_int16_neon(const int16_t *src, int len); void ff_ac3_lshift_int16_neon(int16_t *src, unsigned len, unsigned shift); void ff_ac3_rshift_int32_neon(int32_t *src, unsigned len, unsigned shift); void ff_float_to_fixed24_neon(int32_t *dst, const float *src, unsigned int len); +void ff_ac3_extract_exponents_neon(uint8_t *exp, int32_t *coef, int nb_coefs); void ff_ac3_bit_alloc_calc_bap_armv6(int16_t *mask, int16_t *psd, int start, int end, @@ -50,5 +51,6 @@ av_cold void ff_ac3dsp_init_arm(AC3DSPContext *c, int bit_exact) c->ac3_lshift_int16 = ff_ac3_lshift_int16_neon; c->ac3_rshift_int32 = ff_ac3_rshift_int32_neon; c->float_to_fixed24 = ff_float_to_fixed24_neon; + c->extract_exponents = ff_ac3_extract_exponents_neon; } } diff --git a/libavcodec/arm/ac3dsp_neon.S b/libavcodec/arm/ac3dsp_neon.S index d33d978d7c..946b39f25b 100644 --- a/libavcodec/arm/ac3dsp_neon.S +++ b/libavcodec/arm/ac3dsp_neon.S @@ -92,3 +92,23 @@ function ff_float_to_fixed24_neon, export=1 bgt 1b bx lr endfunc + +function ff_ac3_extract_exponents_neon, export=1 + vmov.i32 q14, #24 + vmov.i32 q15, #8 +1: + vld1.32 {q0}, [r1,:128] + vabs.s32 q1, q0 + vclz.i32 q3, q1 + vsub.i32 q3, q3, q15 + vcge.s32 q2, q3, q14 + vbit q3, q14, q2 + vbic q0, q0, q2 + vmovn.i32 d6, q3 + vmovn.i16 d6, q3 + vst1.32 {q0}, [r1,:128]! + vst1.32 {d6[0]}, [r0,:32]! + subs r2, r2, #4 + bgt 1b + bx lr +endfunc |