diff options
| author | Reimar Döffinger <Reimar.Doeffinger@gmx.de> | 2008-10-20 16:05:29 +0000 |
|---|---|---|
| committer | Reimar Döffinger <Reimar.Doeffinger@gmx.de> | 2008-10-20 16:05:29 +0000 |
| commit | 31c4f07017f54dac8b45147adcd9feee01c1983d (patch) | |
| tree | bb717ce421e27fd1b7c281707563a1610e30eac8 | |
| parent | c8714ea1b39ed25c61f91cbae6930defc3682cc9 (diff) | |
Use x86_reg type instead of long in float_to_int16 MMX/SSE functions.
Fixes compilation on MinGW64.
Originally committed as revision 15655 to svn://svn.ffmpeg.org/ffmpeg/trunk
| -rw-r--r-- | libavcodec/i386/dsputil_mmx.c | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/libavcodec/i386/dsputil_mmx.c b/libavcodec/i386/dsputil_mmx.c index 90691fa20a..78c9e42a8e 100644 --- a/libavcodec/i386/dsputil_mmx.c +++ b/libavcodec/i386/dsputil_mmx.c @@ -2239,6 +2239,7 @@ static void int32_to_float_fmul_scalar_sse2(float *dst, const int *src, float mu } static void float_to_int16_3dnow(int16_t *dst, const float *src, long len){ + x86_reg reglen = len; // not bit-exact: pf2id uses different rounding than C and SSE __asm__ volatile( "add %0 , %0 \n\t" @@ -2257,10 +2258,11 @@ static void float_to_int16_3dnow(int16_t *dst, const float *src, long len){ "add $16 , %0 \n\t" " js 1b \n\t" "femms \n\t" - :"+r"(len), "+r"(dst), "+r"(src) + :"+r"(reglen), "+r"(dst), "+r"(src) ); } static void float_to_int16_sse(int16_t *dst, const float *src, long len){ + x86_reg reglen = len; __asm__ volatile( "add %0 , %0 \n\t" "lea (%2,%0,2) , %2 \n\t" @@ -2278,11 +2280,12 @@ static void float_to_int16_sse(int16_t *dst, const float *src, long len){ "add $16 , %0 \n\t" " js 1b \n\t" "emms \n\t" - :"+r"(len), "+r"(dst), "+r"(src) + :"+r"(reglen), "+r"(dst), "+r"(src) ); } static void float_to_int16_sse2(int16_t *dst, const float *src, long len){ + x86_reg reglen = len; __asm__ volatile( "add %0 , %0 \n\t" "lea (%2,%0,2) , %2 \n\t" @@ -2295,7 +2298,7 @@ static void float_to_int16_sse2(int16_t *dst, const float *src, long len){ "movdqa %%xmm0 , (%1,%0) \n\t" "add $16 , %0 \n\t" " js 1b \n\t" - :"+r"(len), "+r"(dst), "+r"(src) + :"+r"(reglen), "+r"(dst), "+r"(src) ); } @@ -2326,6 +2329,7 @@ static void float_to_int16_interleave_##cpu(int16_t *dst, const float **src, lon if(channels==1)\ float_to_int16_##cpu(dst, src[0], len);\ else if(channels==2){\ + x86_reg reglen = len; \ const float *src0 = src[0];\ const float *src1 = src[1];\ __asm__ volatile(\ @@ -2335,7 +2339,7 @@ static void float_to_int16_interleave_##cpu(int16_t *dst, const float **src, lon "add %0, %3 \n"\ "neg %0 \n"\ body\ - :"+r"(len), "+r"(dst), "+r"(src0), "+r"(src1)\ + :"+r"(reglen), "+r"(dst), "+r"(src0), "+r"(src1)\ );\ }else if(channels==6){\ ff_float_to_int16_interleave6_##cpu(dst, src, len);\ |