From 4e375aa1f536e979a587534df0b6951fa39e8a30 Mon Sep 17 00:00:00 2001
From: Joel Challis <git@zvecr.com>
Date: Tue, 16 Jul 2019 09:30:53 +0100
Subject: Add ARM I2Cv1 support to i2c_master (#6262)

* Add ARM I2Cv1 support to i2c_master

* Add I2Cv1 docs
---
 drivers/arm/i2c_master.c | 11 +++++++++
 drivers/arm/i2c_master.h | 64 +++++++++++++++++++++++++++++++-----------------
 2 files changed, 52 insertions(+), 23 deletions(-)

(limited to 'drivers')

diff --git a/drivers/arm/i2c_master.c b/drivers/arm/i2c_master.c
index 5814375f37..9b4a752b1c 100644
--- a/drivers/arm/i2c_master.c
+++ b/drivers/arm/i2c_master.c
@@ -33,11 +33,17 @@
 static uint8_t i2c_address;
 
 static const I2CConfig i2cconfig = {
+#ifdef USE_I2CV1
+  I2C1_OPMODE,
+  I2C1_CLOCK_SPEED,
+  I2C1_DUTY_CYCLE,
+#else
   STM32_TIMINGR_PRESC(I2C1_TIMINGR_PRESC) |
   STM32_TIMINGR_SCLDEL(I2C1_TIMINGR_SCLDEL) | STM32_TIMINGR_SDADEL(I2C1_TIMINGR_SDADEL) |
   STM32_TIMINGR_SCLH(I2C1_TIMINGR_SCLH)  | STM32_TIMINGR_SCLL(I2C1_TIMINGR_SCLL),
   0,
   0
+#endif
 };
 
 static i2c_status_t chibios_to_qmk(const msg_t* status) {
@@ -61,8 +67,13 @@ void i2c_init(void)
 
   chThdSleepMilliseconds(10);
 
+#ifdef USE_I2CV1
+  palSetPadMode(I2C1_SCL_BANK, I2C1_SCL, PAL_MODE_STM32_ALTERNATE_OPENDRAIN);
+  palSetPadMode(I2C1_SDA_BANK, I2C1_SDA, PAL_MODE_STM32_ALTERNATE_OPENDRAIN);
+#else
   palSetPadMode(I2C1_SCL_BANK, I2C1_SCL, PAL_MODE_ALTERNATE(I2C1_SCL_PAL_MODE) | PAL_STM32_OTYPE_OPENDRAIN);
   palSetPadMode(I2C1_SDA_BANK, I2C1_SDA, PAL_MODE_ALTERNATE(I2C1_SDA_PAL_MODE) | PAL_STM32_OTYPE_OPENDRAIN);
+#endif
 
   //i2cInit(); //This is invoked by halInit() so no need to redo it.
 }
diff --git a/drivers/arm/i2c_master.h b/drivers/arm/i2c_master.h
index 1bb74c800f..2f40d4985f 100644
--- a/drivers/arm/i2c_master.h
+++ b/drivers/arm/i2c_master.h
@@ -22,10 +22,16 @@
  * Please ensure that HAL_USE_I2C is TRUE in the halconf.h file and that
  * STM32_I2C_USE_I2C1 is TRUE in the mcuconf.h file.
  */
+#pragma once
 
 #include "ch.h"
 #include <hal.h>
 
+
+#if defined(STM32F1XX) || defined(STM32F1xx) || defined(STM32F2xx) || defined(STM32F4xx) || defined(STM32L0xx) || defined(STM32L1xx)
+    #define USE_I2CV1
+#endif
+
 #ifdef I2C1_BANK
     #define I2C1_SCL_BANK I2C1_BANK
     #define I2C1_SDA_BANK I2C1_BANK
@@ -46,30 +52,42 @@
     #define I2C1_SDA 7
 #endif
 
-// The default PAL alternate modes are used to signal that the pins are used for I2C
-#ifndef I2C1_SCL_PAL_MODE
-    #define I2C1_SCL_PAL_MODE 4
-#endif
-#ifndef I2C1_SDA_PAL_MODE
-    #define I2C1_SDA_PAL_MODE 4
-#endif
+#ifdef USE_I2CV1
+    #ifndef I2C1_OPMODE
+        #define I2C1_OPMODE OPMODE_I2C
+    #endif
+    #ifndef I2C1_CLOCK_SPEED
+        #define I2C1_CLOCK_SPEED 100000 /* 400000 */
+    #endif
+    #ifndef I2C1_DUTY_CYCLE
+        #define I2C1_DUTY_CYCLE STD_DUTY_CYCLE /* FAST_DUTY_CYCLE_2 */
+    #endif
+#else
+    // The default PAL alternate modes are used to signal that the pins are used for I2C
+    #ifndef I2C1_SCL_PAL_MODE
+        #define I2C1_SCL_PAL_MODE 4
+    #endif
+    #ifndef I2C1_SDA_PAL_MODE
+        #define I2C1_SDA_PAL_MODE 4
+    #endif
 
-// The default timing values below configures the I2C clock to 400khz assuming a 72Mhz clock
-// For more info : https://www.st.com/en/embedded-software/stsw-stm32126.html
-#ifndef I2C1_TIMINGR_PRESC
-    #define I2C1_TIMINGR_PRESC 15U
-#endif
-#ifndef I2C1_TIMINGR_SCLDEL
-    #define I2C1_TIMINGR_SCLDEL 4U
-#endif
-#ifndef I2C1_TIMINGR_SDADEL
-    #define I2C1_TIMINGR_SDADEL 2U
-#endif
-#ifndef I2C1_TIMINGR_SCLH
-    #define I2C1_TIMINGR_SCLH 15U
-#endif
-#ifndef I2C1_TIMINGR_SCLL
-    #define I2C1_TIMINGR_SCLL 21U
+    // The default timing values below configures the I2C clock to 400khz assuming a 72Mhz clock
+    // For more info : https://www.st.com/en/embedded-software/stsw-stm32126.html
+    #ifndef I2C1_TIMINGR_PRESC
+        #define I2C1_TIMINGR_PRESC 15U
+    #endif
+    #ifndef I2C1_TIMINGR_SCLDEL
+        #define I2C1_TIMINGR_SCLDEL 4U
+    #endif
+    #ifndef I2C1_TIMINGR_SDADEL
+        #define I2C1_TIMINGR_SDADEL 2U
+    #endif
+    #ifndef I2C1_TIMINGR_SCLH
+        #define I2C1_TIMINGR_SCLH 15U
+    #endif
+    #ifndef I2C1_TIMINGR_SCLL
+        #define I2C1_TIMINGR_SCLL 21U
+    #endif
 #endif
 
 #ifndef I2C_DRIVER
-- 
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