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author | RĂ©mi Denis-Courmont <remi@remlab.net> | 2022-10-02 14:54:58 +0300 |
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committer | Lynne <dev@lynne.ee> | 2022-10-05 08:26:19 +0200 |
commit | 37d5ddc317c35bded22fee8d79020653781d8230 (patch) | |
tree | 0e4162777730cfeea45976bda4fa350af573b5a5 /tests | |
parent | b25c6a5704ac114e825577209a610f5e95abe6c0 (diff) |
lavu/riscv: CPU flag for the Zbb extension
Unfortunately, it is common, and will remain so, that the Bit
manipulations are not enabled at compilation time. This is an official
policy for Debian ports in general (though they do not support RISC-V
officially as of yet) to stick to the minimal target baseline, which
does not include the B extension or even its Zbb subset.
For inline helpers (CPOP, REV8), compiler builtins (CTZ, CLZ) or
even plain C code (MIN, MAX, MINU, MAXU), run-time detection seems
impractical. But at least it can work for the byte-swap DSP functions.
Diffstat (limited to 'tests')
-rw-r--r-- | tests/checkasm/checkasm.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/tests/checkasm/checkasm.c b/tests/checkasm/checkasm.c index 90dd7e4634..421bd096c5 100644 --- a/tests/checkasm/checkasm.c +++ b/tests/checkasm/checkasm.c @@ -240,6 +240,7 @@ static const struct { { "RVVf32", "rvv_f32", AV_CPU_FLAG_RVV_F32 }, { "RVVi64", "rvv_i64", AV_CPU_FLAG_RVV_I64 }, { "RVVf64", "rvv_f64", AV_CPU_FLAG_RVV_F64 }, + { "RVBbasic", "rvb_b", AV_CPU_FLAG_RVB_BASIC }, #elif ARCH_MIPS { "MMI", "mmi", AV_CPU_FLAG_MMI }, { "MSA", "msa", AV_CPU_FLAG_MSA }, |