diff options
| author | Rémi Denis-Courmont <remi@remlab.net> | 2023-07-16 15:08:08 +0300 |
|---|---|---|
| committer | Rémi Denis-Courmont <remi@remlab.net> | 2023-07-19 19:29:35 +0300 |
| commit | b6585eb04c0f63f231ed16266c6ad893522dc750 (patch) | |
| tree | bc10e79af8332dd8c925a5fafa5546450c3e3b88 /libswscale/riscv | |
| parent | 98e4dd39c5d59d62f61f48f6e4a0192f6b46e5aa (diff) | |
lavu: add/use flag for RISC-V Zba extension
The code was blindly assuming that Zbb or V implied Zba. While the
earlier is practically always true, the later broke some QEMU setups,
as V was introduced earlier than Zba.
Diffstat (limited to 'libswscale/riscv')
| -rw-r--r-- | libswscale/riscv/rgb2rgb.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/libswscale/riscv/rgb2rgb.c b/libswscale/riscv/rgb2rgb.c index 37a2cd5ea1..4c2d0f07d2 100644 --- a/libswscale/riscv/rgb2rgb.c +++ b/libswscale/riscv/rgb2rgb.c @@ -45,7 +45,7 @@ av_cold void rgb2rgb_init_riscv(void) #if HAVE_RVV int flags = av_get_cpu_flags(); - if (flags & AV_CPU_FLAG_RVV_I32) { + if ((flags & AV_CPU_FLAG_RVV_I32) && (flags & AV_CPU_FLAG_RVB_ADDR)) { shuffle_bytes_0321 = ff_shuffle_bytes_0321_rvv; shuffle_bytes_2103 = ff_shuffle_bytes_2103_rvv; shuffle_bytes_1230 = ff_shuffle_bytes_1230_rvv; |