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authorDiego Biurrun <diego@biurrun.de>2012-07-08 18:42:12 +0200
committerDiego Biurrun <diego@biurrun.de>2012-08-03 22:51:05 +0200
commit239fdf1b4a3dd9decad157d4694837cffa917021 (patch)
treea92ed88dd8a7bf975f10ff638f1fa2d256de657e /libavutil
parent66adb7ce1bc1cc5e3f1c4b1cd9f20ac68086a486 (diff)
x86: build: replace mmx2 by mmxext
Refactoring mmx2/mmxext YASM code with cpuflags will force renames. So switching to a consistent naming scheme beforehand is sensible. The name "mmxext" is more official and widespread and also the name of the CPU flag, as reported e.g. by the Linux kernel.
Diffstat (limited to 'libavutil')
-rw-r--r--libavutil/cpu.c8
-rw-r--r--libavutil/cpu.h5
-rw-r--r--libavutil/version.h2
-rw-r--r--libavutil/x86/cpu.c4
4 files changed, 12 insertions, 7 deletions
diff --git a/libavutil/cpu.c b/libavutil/cpu.c
index c641106fff..1fb40511ff 100644
--- a/libavutil/cpu.c
+++ b/libavutil/cpu.c
@@ -47,10 +47,10 @@ void av_set_cpu_flags_mask(int mask)
int av_parse_cpu_flags(const char *s)
{
-#define CPUFLAG_MMX2 (AV_CPU_FLAG_MMX | AV_CPU_FLAG_MMX2 | AV_CPU_FLAG_CMOV)
+#define CPUFLAG_MMXEXT (AV_CPU_FLAG_MMX | AV_CPU_FLAG_MMXEXT | AV_CPU_FLAG_CMOV)
#define CPUFLAG_3DNOW (AV_CPU_FLAG_3DNOW | AV_CPU_FLAG_MMX)
#define CPUFLAG_3DNOWEXT (AV_CPU_FLAG_3DNOWEXT | CPUFLAG_3DNOW)
-#define CPUFLAG_SSE (AV_CPU_FLAG_SSE | CPUFLAG_MMX2)
+#define CPUFLAG_SSE (AV_CPU_FLAG_SSE | CPUFLAG_MMXEXT)
#define CPUFLAG_SSE2 (AV_CPU_FLAG_SSE2 | CPUFLAG_SSE)
#define CPUFLAG_SSE2SLOW (AV_CPU_FLAG_SSE2SLOW | CPUFLAG_SSE2)
#define CPUFLAG_SSE3 (AV_CPU_FLAG_SSE3 | CPUFLAG_SSE2)
@@ -67,7 +67,7 @@ int av_parse_cpu_flags(const char *s)
{ "altivec" , NULL, 0, AV_OPT_TYPE_CONST, { AV_CPU_FLAG_ALTIVEC }, .unit = "flags" },
#elif ARCH_X86
{ "mmx" , NULL, 0, AV_OPT_TYPE_CONST, { AV_CPU_FLAG_MMX }, .unit = "flags" },
- { "mmx2" , NULL, 0, AV_OPT_TYPE_CONST, { CPUFLAG_MMX2 }, .unit = "flags" },
+ { "mmxext" , NULL, 0, AV_OPT_TYPE_CONST, { CPUFLAG_MMXEXT }, .unit = "flags" },
{ "sse" , NULL, 0, AV_OPT_TYPE_CONST, { CPUFLAG_SSE }, .unit = "flags" },
{ "sse2" , NULL, 0, AV_OPT_TYPE_CONST, { CPUFLAG_SSE2 }, .unit = "flags" },
{ "sse2slow", NULL, 0, AV_OPT_TYPE_CONST, { CPUFLAG_SSE2SLOW }, .unit = "flags" },
@@ -129,7 +129,7 @@ static const struct {
{ AV_CPU_FLAG_ALTIVEC, "altivec" },
#elif ARCH_X86
{ AV_CPU_FLAG_MMX, "mmx" },
- { AV_CPU_FLAG_MMX2, "mmx2" },
+ { AV_CPU_FLAG_MMXEXT, "mmxext" },
{ AV_CPU_FLAG_SSE, "sse" },
{ AV_CPU_FLAG_SSE2, "sse2" },
{ AV_CPU_FLAG_SSE2SLOW, "sse2(slow)" },
diff --git a/libavutil/cpu.h b/libavutil/cpu.h
index f477c83e13..01f7201a5e 100644
--- a/libavutil/cpu.h
+++ b/libavutil/cpu.h
@@ -21,11 +21,16 @@
#ifndef AVUTIL_CPU_H
#define AVUTIL_CPU_H
+#include "version.h"
+
#define AV_CPU_FLAG_FORCE 0x80000000 /* force usage of selected flags (OR) */
/* lower 16 bits - CPU features */
#define AV_CPU_FLAG_MMX 0x0001 ///< standard MMX
+#define AV_CPU_FLAG_MMXEXT 0x0002 ///< SSE integer functions or AMD MMX ext
+#if LIBAVUTIL_VERSION_MAJOR < 52
#define AV_CPU_FLAG_MMX2 0x0002 ///< SSE integer functions or AMD MMX ext
+#endif
#define AV_CPU_FLAG_3DNOW 0x0004 ///< AMD 3DNOW
#define AV_CPU_FLAG_SSE 0x0008 ///< SSE functions
#define AV_CPU_FLAG_SSE2 0x0010 ///< PIV SSE2 functions
diff --git a/libavutil/version.h b/libavutil/version.h
index f55a99fd48..bd60d3f282 100644
--- a/libavutil/version.h
+++ b/libavutil/version.h
@@ -38,7 +38,7 @@
#define LIBAVUTIL_VERSION_MAJOR 51
#define LIBAVUTIL_VERSION_MINOR 37
-#define LIBAVUTIL_VERSION_MICRO 0
+#define LIBAVUTIL_VERSION_MICRO 1
#define LIBAVUTIL_VERSION_INT AV_VERSION_INT(LIBAVUTIL_VERSION_MAJOR, \
LIBAVUTIL_VERSION_MINOR, \
diff --git a/libavutil/x86/cpu.c b/libavutil/x86/cpu.c
index d3b1bd5ea6..a63b564985 100644
--- a/libavutil/x86/cpu.c
+++ b/libavutil/x86/cpu.c
@@ -122,7 +122,7 @@ int ff_get_cpu_flags_x86(void)
if (std_caps & (1 << 23))
rval |= AV_CPU_FLAG_MMX;
if (std_caps & (1 << 25))
- rval |= AV_CPU_FLAG_MMX2;
+ rval |= AV_CPU_FLAG_MMXEXT;
#if HAVE_SSE
if (std_caps & (1 << 25))
rval |= AV_CPU_FLAG_SSE;
@@ -159,7 +159,7 @@ int ff_get_cpu_flags_x86(void)
if (ext_caps & (1 << 23))
rval |= AV_CPU_FLAG_MMX;
if (ext_caps & (1 << 22))
- rval |= AV_CPU_FLAG_MMX2;
+ rval |= AV_CPU_FLAG_MMXEXT;
/* Allow for selectively disabling SSE2 functions on AMD processors
with SSE2 support but not SSE4a. This includes Athlon64, some