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| author | Michael Niedermayer <michaelni@gmx.at> | 2012-08-04 22:39:25 +0200 |
|---|---|---|
| committer | Michael Niedermayer <michaelni@gmx.at> | 2012-08-04 23:51:43 +0200 |
| commit | e776ee8f294984f7643a3c45db803c7266e1edfd (patch) | |
| tree | a1fd00ab7a0760ec0f2848aed9dc3f79d889e816 /libavutil/x86/cpu.c | |
| parent | 88fc1438c693ffb7793aeb111d89775440491840 (diff) | |
| parent | 8821ae649e61097ec57ca58472c3e4239c82913c (diff) | |
Merge remote-tracking branch 'qatar/master'
* qatar/master:
lavr: fix handling of custom mix matrices
fate: force pix_fmt in lagarith-rgb32 test
fate: add tests for lagarith lossless video codec.
ARMv6: vp8: fix stack allocation with Apple's assembler
ARM: vp56: allow inline asm to build with clang
fft: 3dnow: fix register name typo in DECL_IMDCT macro
x86: dct32: port to cpuflags
x86: build: replace mmx2 by mmxext
Revert "wmapro: prevent division by zero when sample rate is unspecified"
wmapro: prevent division by zero when sample rate is unspecified
lagarith: fix color plane inversion for YUY2 output.
lagarith: pad RGB buffer by 1 byte.
dsputil: make add_hfyu_left_prediction_sse4() support unaligned src.
Conflicts:
doc/APIchanges
libavcodec/lagarith.c
libavfilter/x86/gradfun.c
libavutil/cpu.h
libavutil/version.h
libswscale/utils.c
libswscale/version.h
libswscale/x86/yuv2rgb.c
Merged-by: Michael Niedermayer <michaelni@gmx.at>
Diffstat (limited to 'libavutil/x86/cpu.c')
| -rw-r--r-- | libavutil/x86/cpu.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/libavutil/x86/cpu.c b/libavutil/x86/cpu.c index b1052247a0..7b31f2a88a 100644 --- a/libavutil/x86/cpu.c +++ b/libavutil/x86/cpu.c @@ -122,7 +122,7 @@ int ff_get_cpu_flags_x86(void) if (std_caps & (1 << 23)) rval |= AV_CPU_FLAG_MMX; if (std_caps & (1 << 25)) - rval |= AV_CPU_FLAG_MMX2; + rval |= AV_CPU_FLAG_MMXEXT; #if HAVE_SSE if (std_caps & (1 << 25)) rval |= AV_CPU_FLAG_SSE; @@ -159,7 +159,7 @@ int ff_get_cpu_flags_x86(void) if (ext_caps & (1 << 23)) rval |= AV_CPU_FLAG_MMX; if (ext_caps & (1 << 22)) - rval |= AV_CPU_FLAG_MMX2; + rval |= AV_CPU_FLAG_MMXEXT; /* Allow for selectively disabling SSE2 functions on AMD processors with SSE2 support but not SSE4a. This includes Athlon64, some |