diff options
| author | Mans Rullgard <mans@mansr.com> | 2011-03-13 02:21:33 +0000 |
|---|---|---|
| committer | Mans Rullgard <mans@mansr.com> | 2011-07-06 00:29:59 +0100 |
| commit | a4928cf380634fd75761405169ac73e696caaf11 (patch) | |
| tree | be82b23b74ec2aefb84143822b65fd5cb186c691 /libavcodec/arm | |
| parent | f507a9fe002c6a444cbd38a1326ee4f9df8c10a1 (diff) | |
ac3enc: neon optimised sum_square_butterfly_int32
Diffstat (limited to 'libavcodec/arm')
| -rw-r--r-- | libavcodec/arm/ac3dsp_init_arm.c | 5 | ||||
| -rw-r--r-- | libavcodec/arm/ac3dsp_neon.S | 24 |
2 files changed, 29 insertions, 0 deletions
diff --git a/libavcodec/arm/ac3dsp_init_arm.c b/libavcodec/arm/ac3dsp_init_arm.c index aed11f4bb8..2a100a708a 100644 --- a/libavcodec/arm/ac3dsp_init_arm.c +++ b/libavcodec/arm/ac3dsp_init_arm.c @@ -29,6 +29,10 @@ void ff_ac3_lshift_int16_neon(int16_t *src, unsigned len, unsigned shift); void ff_ac3_rshift_int32_neon(int32_t *src, unsigned len, unsigned shift); void ff_float_to_fixed24_neon(int32_t *dst, const float *src, unsigned int len); void ff_ac3_extract_exponents_neon(uint8_t *exp, int32_t *coef, int nb_coefs); +void ff_ac3_sum_square_butterfly_int32_neon(int64_t sum[4], + const int32_t *coef0, + const int32_t *coef1, + int len); void ff_ac3_bit_alloc_calc_bap_armv6(int16_t *mask, int16_t *psd, int start, int end, @@ -52,5 +56,6 @@ av_cold void ff_ac3dsp_init_arm(AC3DSPContext *c, int bit_exact) c->ac3_rshift_int32 = ff_ac3_rshift_int32_neon; c->float_to_fixed24 = ff_float_to_fixed24_neon; c->extract_exponents = ff_ac3_extract_exponents_neon; + c->sum_square_butterfly_int32 = ff_ac3_sum_square_butterfly_int32_neon; } } diff --git a/libavcodec/arm/ac3dsp_neon.S b/libavcodec/arm/ac3dsp_neon.S index e97197c27a..a15fbbcfa1 100644 --- a/libavcodec/arm/ac3dsp_neon.S +++ b/libavcodec/arm/ac3dsp_neon.S @@ -108,3 +108,27 @@ function ff_ac3_extract_exponents_neon, export=1 bgt 1b bx lr endfunc + +function ff_ac3_sum_square_butterfly_int32_neon, export=1 + vmov.i64 q0, #0 + vmov.i64 q1, #0 + vmov.i64 q2, #0 + vmov.i64 q3, #0 +1: + vld1.32 {d16}, [r1]! + vld1.32 {d17}, [r2]! + vadd.s32 d18, d16, d17 + vsub.s32 d19, d16, d17 + vmlal.s32 q0, d16, d16 + vmlal.s32 q1, d17, d17 + vmlal.s32 q2, d18, d18 + vmlal.s32 q3, d19, d19 + subs r3, r3, #2 + bgt 1b + vadd.s64 d0, d0, d1 + vadd.s64 d1, d2, d3 + vadd.s64 d2, d4, d5 + vadd.s64 d3, d6, d7 + vst1.64 {q0-q1}, [r0] + bx lr +endfunc |