diff options
| author | Mans Rullgard <mans@mansr.com> | 2011-06-14 11:29:48 +0100 |
|---|---|---|
| committer | Mans Rullgard <mans@mansr.com> | 2011-06-23 07:31:54 +0100 |
| commit | 8986fddc2bab92bd7d77a123ac70c4fb70c96c7c (patch) | |
| tree | 73b8c4a57c98be10d4403dc69ec3019a1665b3f0 /libavcodec/arm/vp8_armv6.S | |
| parent | 9cd7b8549b71bcfced2062596fd9eecba092aeb1 (diff) | |
ARM: allow building in Thumb2 mode
Signed-off-by: Mans Rullgard <mans@mansr.com>
Diffstat (limited to 'libavcodec/arm/vp8_armv6.S')
| -rw-r--r-- | libavcodec/arm/vp8_armv6.S | 36 |
1 files changed, 33 insertions, 3 deletions
diff --git a/libavcodec/arm/vp8_armv6.S b/libavcodec/arm/vp8_armv6.S index 602c8a58be..1d89c68909 100644 --- a/libavcodec/arm/vp8_armv6.S +++ b/libavcodec/arm/vp8_armv6.S @@ -25,13 +25,18 @@ lsl \cw, \cw, \t0 lsl \t0, \h, \t0 rsb \h, \pr, #256 + it cs ldrhcs \t1, [\buf], #2 smlabb \h, \t0, \pr, \h +T itttt cs rev16cs \t1, \t1 - orrcs \cw, \cw, \t1, lsl \bs +A orrcs \cw, \cw, \t1, lsl \bs +T lslcs \t1, \t1, \bs +T orrcs \cw, \cw, \t1 subcs \bs, \bs, #16 lsr \h, \h, #8 cmp \cw, \h, lsl #16 + itt ge subge \cw, \cw, \h, lsl #16 subge \h, \t0, \h .endm @@ -40,14 +45,20 @@ adds \bs, \bs, \t0 lsl \cw, \cw, \t0 lsl \t0, \h, \t0 + it cs ldrhcs \t1, [\buf], #2 mov \h, #128 + it cs rev16cs \t1, \t1 add \h, \h, \t0, lsl #7 - orrcs \cw, \cw, \t1, lsl \bs +A orrcs \cw, \cw, \t1, lsl \bs +T ittt cs +T lslcs \t1, \t1, \bs +T orrcs \cw, \cw, \t1 subcs \bs, \bs, #16 lsr \h, \h, #8 cmp \cw, \h, lsl #16 + itt ge subge \cw, \cw, \h, lsl #16 subge \h, \t0, \h .endm @@ -59,6 +70,7 @@ function ff_decode_block_coeffs_armv6, export=1 cmp r3, #0 ldr r11, [r5] ldm r0, {r5-r7} @ high, bits, buf + it ne pkhtbne r11, r11, r11, asr #16 ldr r8, [r0, #16] @ code_word 0: @@ -80,19 +92,26 @@ function ff_decode_block_coeffs_armv6, export=1 adds r6, r6, r9 add r4, r4, #11 lsl r8, r8, r9 + it cs ldrhcs r10, [r7], #2 lsl r9, r5, r9 mov r5, #128 + it cs rev16cs r10, r10 add r5, r5, r9, lsl #7 - orrcs r8, r8, r10, lsl r6 +T ittt cs +T lslcs r10, r10, r6 +T orrcs r8, r8, r10 +A orrcs r8, r8, r10, lsl r6 subcs r6, r6, #16 lsr r5, r5, #8 cmp r8, r5, lsl #16 movrel r10, zigzag_scan-1 + itt ge subge r8, r8, r5, lsl #16 subge r5, r9, r5 ldrb r10, [r10, r3] + it ge rsbge r12, r12, #0 cmp r3, #16 strh r12, [r1, r10] @@ -108,6 +127,7 @@ function ff_decode_block_coeffs_armv6, export=1 ldr r0, [sp] ldr r9, [r0, #12] cmp r7, r9 + it hi movhi r7, r9 stm r0, {r5-r7} @ high, bits, buf str r8, [r0, #16] @ code_word @@ -131,11 +151,13 @@ function ff_decode_block_coeffs_armv6, export=1 mov r12, #2 ldrb r0, [r4, #4] rac_get_prob r5, r6, r7, r8, r0, r9, r10 + it ge addge r12, #1 ldrb r9, [lr, r5] blt 4f ldrb r0, [r4, #5] rac_get_prob r5, r6, r7, r8, r0, r9, r10 + it ge addge r12, #1 ldrb r9, [lr, r5] b 4f @@ -153,6 +175,7 @@ function ff_decode_block_coeffs_armv6, export=1 mov r12, #5 mov r0, #159 rac_get_prob r5, r6, r7, r8, r0, r9, r10 + it ge addge r12, r12, #1 ldrb r9, [lr, r5] b 4f @@ -160,23 +183,28 @@ function ff_decode_block_coeffs_armv6, export=1 mov r12, #7 mov r0, #165 rac_get_prob r5, r6, r7, r8, r0, r9, r10 + it ge addge r12, r12, #2 ldrb r9, [lr, r5] mov r0, #145 rac_get_prob r5, r6, r7, r8, r0, r9, r10 + it ge addge r12, r12, #1 ldrb r9, [lr, r5] b 4f 3: ldrb r0, [r4, #8] rac_get_prob r5, r6, r7, r8, r0, r9, r10 + it ge addge r4, r4, #1 ldrb r9, [lr, r5] + ite ge movge r12, #2 movlt r12, #0 ldrb r0, [r4, #9] rac_get_prob r5, r6, r7, r8, r0, r9, r10 mov r9, #8 + it ge addge r12, r12, #1 movrel r4, X(ff_vp8_dct_cat_prob) lsl r9, r9, r12 @@ -189,6 +217,7 @@ function ff_decode_block_coeffs_armv6, export=1 lsl r1, r1, #1 rac_get_prob r5, r6, r7, r8, r0, r9, r10 ldrb r0, [r4], #1 + it ge addge r1, r1, #1 cmp r0, #0 bne 1b @@ -200,6 +229,7 @@ function ff_decode_block_coeffs_armv6, export=1 add r4, r2, r4 add r4, r4, #22 rac_get_128 r5, r6, r7, r8, r9, r10 + it ge rsbge r12, r12, #0 smulbb r12, r12, r11 movrel r9, zigzag_scan-1 |