diff options
| author | Mans Rullgard <mans@mansr.com> | 2011-06-14 11:29:48 +0100 |
|---|---|---|
| committer | Mans Rullgard <mans@mansr.com> | 2011-06-23 07:31:54 +0100 |
| commit | 8986fddc2bab92bd7d77a123ac70c4fb70c96c7c (patch) | |
| tree | 73b8c4a57c98be10d4403dc69ec3019a1665b3f0 /libavcodec/arm/vp56_arith.h | |
| parent | 9cd7b8549b71bcfced2062596fd9eecba092aeb1 (diff) | |
ARM: allow building in Thumb2 mode
Signed-off-by: Mans Rullgard <mans@mansr.com>
Diffstat (limited to 'libavcodec/arm/vp56_arith.h')
| -rw-r--r-- | libavcodec/arm/vp56_arith.h | 27 |
1 files changed, 23 insertions, 4 deletions
diff --git a/libavcodec/arm/vp56_arith.h b/libavcodec/arm/vp56_arith.h index 9ce3fd0d91..ef30ffe897 100644 --- a/libavcodec/arm/vp56_arith.h +++ b/libavcodec/arm/vp56_arith.h @@ -21,6 +21,14 @@ #ifndef AVCODEC_ARM_VP56_ARITH_H #define AVCODEC_ARM_VP56_ARITH_H +#if CONFIG_THUMB +# define A(x) +# define T(x) x +#else +# define A(x) x +# define T(x) +#endif + #if HAVE_ARMV6 && HAVE_INLINE_ASM #define vp56_rac_get_prob vp56_rac_get_prob_armv6 @@ -32,15 +40,21 @@ static inline int vp56_rac_get_prob_armv6(VP56RangeCoder *c, int pr) unsigned bit; __asm__ ("adds %3, %3, %0 \n" + "itt cs \n" "cmpcs %7, %4 \n" - "ldrcsh %2, [%4], #2 \n" + A("ldrcsh %2, [%4], #2 \n") + T("ldrhcs %2, [%4], #2 \n") "rsb %0, %6, #256 \n" "smlabb %0, %5, %6, %0 \n" + T("itttt cs \n") "rev16cs %2, %2 \n" - "orrcs %1, %1, %2, lsl %3 \n" + T("lslcs %2, %2, %3 \n") + T("orrcs %1, %1, %2 \n") + A("orrcs %1, %1, %2, lsl %3 \n") "subcs %3, %3, #16 \n" "lsr %0, %0, #8 \n" "cmp %1, %0, lsl #16 \n" + "ittte ge \n" "subge %1, %1, %0, lsl #16 \n" "subge %0, %5, %0 \n" "movge %2, #1 \n" @@ -64,12 +78,17 @@ static inline int vp56_rac_get_prob_branchy_armv6(VP56RangeCoder *c, int pr) unsigned tmp; __asm__ ("adds %3, %3, %0 \n" + "itt cs \n" "cmpcs %7, %4 \n" - "ldrcsh %2, [%4], #2 \n" + A("ldrcsh %2, [%4], #2 \n") + T("ldrhcs %2, [%4], #2 \n") "rsb %0, %6, #256 \n" "smlabb %0, %5, %6, %0 \n" + T("itttt cs \n") "rev16cs %2, %2 \n" - "orrcs %1, %1, %2, lsl %3 \n" + T("lslcs %2, %2, %3 \n") + T("orrcs %1, %1, %2 \n") + A("orrcs %1, %1, %2, lsl %3 \n") "subcs %3, %3, #16 \n" "lsr %0, %0, #8 \n" "lsl %2, %0, #16 \n" |