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author | RĂ©mi Denis-Courmont <remi@remlab.net> | 2022-09-12 18:53:16 +0300 |
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committer | James Almer <jamrial@gmail.com> | 2022-09-13 16:50:43 -0300 |
commit | 092ce9712f63fc2641ec831d09c8ca0731083ae4 (patch) | |
tree | a45e830c24538a5ab7f7cb5c9c7332b95ce52fd4 | |
parent | bda3a9faf4a2f201b24fb38a04da86410c9205ae (diff) |
doc: reference the RISC-V specification
-rw-r--r-- | doc/optimization.txt | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/doc/optimization.txt b/doc/optimization.txt index 974e2f9af2..3ed29fe38c 100644 --- a/doc/optimization.txt +++ b/doc/optimization.txt @@ -267,6 +267,11 @@ CELL/SPU: http://www-01.ibm.com/chips/techlib/techlib.nsf/techdocs/30B3520C93F437AB87257060006FFE5E/$file/Language_Extensions_for_CBEA_2.4.pdf http://www-01.ibm.com/chips/techlib/techlib.nsf/techdocs/9F820A5FFA3ECE8C8725716A0062585F/$file/CBE_Handbook_v1.1_24APR2007_pub.pdf +RISC-V-specific: +---------------- +The RISC-V Instruction Set Manual, Volume 1, Unprivileged ISA: +https://riscv.org/technical/specifications/ + GCC asm links: -------------- official doc but quite ugly |